With the growing amount of data to be transmitted and the increasing number of data channels which have to be supported, fast switching of information becomes more and more an important task in any communication network. The network nodes in which lines or transmission links are interconnected so that information may be exchanged between them are often cause of delay in the network. It is therefore desirable to have switching elements being fast and practically non-blocking. New possibilities are given by switch fabrics interconnecting several inputs and outputs. The advantages made in switching technology allow the construction of switch fabrics for wideband band and high speed communication.
These switches must perform two basic functions at high speed. First, they have to route the traffic arriving on its inputs to the appropriate outputs with high reliability. Second, the switch must deal with output contention, where traffic arriving at the same time on two or more inputs may be destined for a common output.
With circuit switching, output contention is no problem as a controller is used to schedule arrivals and avoid conflicts. With packet switching, however, packets arriving at a switch are unscheduled, each containing a header with address information. Without the coordination by a central scheduler, the received packets have to be buffered to prevent problems at the outputs. A descriptive overview of the major recent activities on the field of packet switches is given by an article of H. Ahmadi et al., "A Survey of Modern High-Performance Switching Techniques", IEEE J. SAC, Vol. 7, No. 7, September 1989, pp. 1091-1103. A typical packet switch is described in the article "The Knockout Switch: A Simple, Modular Architecture For High-Performance Packet Switching", of Y. S. Yeh et al., XII International Switching Symposium ISS'87, Phoenix, Ariz. USA, Mar. 15-20, 1987, paper B10.2, or in the article "The Knockout Switch: A Simple, Modular Architecture For High-Performance Packet Switching", of the same authors, IEEE Journal on Selected Areas in Communication, Vol. SAC-5, No. 8, October 1987, pp. 1274-1283. The switching element described by Yeh et al. comprises a `concentrator` to concentrate the packets arriving on the N input lines onto a smaller number of L lines. A `round robin server` is used to take the packets from the L output lines and store them in the first available FIFO buffer connected to the output to which the packet is directed. L separate FIFO buffers are used in the design to cater for the worst possible case that one time slot L packets emerge from the concentrator. Another example of a packet switch is the buffered Fast Packet Switching module described in "Packet Switching Module", W. Denzel et al., IBM Technical Disclosure Bulletin, Vol. 32, No. 10B, March 1990, pp. 176-177. In this switch, the destination headers are separated on arrival in the switch from the data packets. These packets are stored in a specified address within a packet buffer memory and then this buffer address is passed through the control section of the packet switching module. At the outputs of the switch, the buffer address is used to retrieve the data packet from the packet buffer memory.
Most of the recent proposals for those high-performance switching fabrics have been based on the principle known as fast packet switching (FPS). As described in the above cited Technical Disclosure Bulletin article, a high degree of parallelism, distributed control, and routing performed on the hardware level is necessary for these kind of switches. For the employment of these switches in communication networks, data have to be adapted to the underlying cell structure of the switch.
The Packet Switching Module, as referenced above, transports data in fixed length cells from the inputs to the outputs. One example for a fixed length cell is an ATM cell consisting of a header and a cell data field. For the usage of this switch in different systems an adapter has to be employed which transports data frames, as sent by a user, through said switch.
The present invention relates to a method for transforming user frames into fixed length cells and for re-assembling fixed length cells to the original user frames. Data sent by a user are segmented into fixed length cells, as required by the switch fabric, transported through the switch and re-assembled at its output. A hardware implementation of this method, as hereinafter described, comprises two parts called transmitter and receiver. This transmitter is receiving user data segments them into fixed length cells and transmits them to the switch fabric. These fixed length cells are routed through the switch and received by said receiver, which re-assembles these cells into user frames. The transmitter, switch fabric, and receiver are part of a switching subsystem, such that a user is sending user frames to the switch without knowing the underlying transport mechanism.